There is a class of metal-insulator-silicon (MIS) devices in which the gate is formed in a trench that extends downward from the surface of the silicon or other semiconductor material. The current flow in such devices is primarily vertical and as a result the cells can be more densely packed. All else being equal, this increases the current carrying capability and reduces the on-resistance of the device. Devices that fit into the general catagory of MIS devices include metal-oxide-silicon field-effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs) and MOS-gated thyristors. Cross-sectional views of a single gate trench in a MOSFET, an IGBT and a MOS-gated thyristor are shown in FIGS. 1, 2 and 3, respectively.
In such devices the gate material, often polysilicon, must be connected to the leads of the device package and to external circuitry by means of a conductive pad, typically metal. To accomplish this, the trench is filled to overflowing with the gate material and the gate material is patterned using lithography and etching. Following the patterning, the gate material normally is restricted to the inside of the trench in the active areas of the device, as shown in FIGS. 1, 2 and 3. In the areas where the contact is to be made to the gate material, however, the gate material extends outside of the trench and overlies the surface of the silicon. This is shown in the three-dimensional cutaway view of a conventional MIS device 40 in FIG. 4, wherein in an inactive gate metal area 41 a polysilicon layer 42 extends outside the trenches 44 and overlies the epitaxial silicon layer 46. Trenches 44 are lined with a gate oxide layer 47 which insulates the polysilicon layer 42 from the epitaxial layer 46. The ends of the trenches are designated 43. A portion of the polysilicon layer 42 overlies a thick field oxide region 48. The area of contact between a subsequent gate metal layer and polysilicon layer 42 is designated 45.
FIG. 5A is a top view of the gate metal area 41 of the same device. FIG. 5B is a cross-sectional view of the same device taken at cross-section 5B-5B (drawn to a different scale from FIG. 5A). In this embodiment the MIS cells 54 in the active area 56 are square. Polysilicon layer 42 and the area of contact 45 between gate metal 49 and polysilicon layer 42 are shown. FIG. 6 is a similar top view taken in the gate pad edge and termination region of the device.
The corners of the trenches are known to be sources of stress, leading to defect-related problems in devices. This is shown in FIG. 7, which is a detailed cross-sectional view taken near the end of one of trenches 44. The upper trench corners, represented by 52, typically oxidize in a manner that leads to local thinning of the oxide and a lower breakdown voltage across the oxide. The sharper the corner, the more serious this problem becomes. Moreover, when a voltage difference is applied between the gate and the adjacent semiconductor material (P-body in FIG. 7, which in a MOSFET is normally shorted to the source), the electric field reaches a maximum at the trench corners as a result of field crowding. This leads to leakage currents from Fowler-Nordheim tunneling through the gate oxide and limits the maximum usable gate voltage of the device. The field-crowding problem is present even if the gate oxide layer is perfectly uniform, and it becomes worse as the trench corner becomes sharper.
For these reasons, many manufacturers use various techniques for rounding the trench corners. It is difficult, however, to round the upper trench corners sufficiently to avoid the problem of an excessive gate leakage current, and it is likely to become more difficult to do so as cell densities increase.
Furthermore, the process used to fabricate trench-gated MOSFETs normally involves many mask steps and yields an uneven topography that hinders the definition of very small features. FIGS. 8A-8I illustrate the steps of a conventional process performed on an N+ silicon substrate 802. The process begins with a first photoresist mask A1 which is formed over an oxide layer 804 and patterned, using normal photolithographic processes, to define the areas where P-tubs will be formed (FIG. 8A). The P-tubs are used to reduce the strength of the electric field at the corners of the trenches. P-type dopant is implant through openings in mask A1 to form P-tubs 806, and mask A1 is removed. After P-tubs 806 are driven in by heating, which thickens oxide layer 804 (FIG. 8B), a second mask A2 is deposited and patterned to define the active region 808 of the device, the oxide layer 804, which has become a field oxide layer, remaining in a termination region 810 of the device (FIG. 8C).
Mask A2 is removed, and a third, trench mask A3 is formed and patterned to define where the trenches will be located. Trenches 812 are then etched, typically using a reactive ion etch (RIE) process (FIG. 8D). Trenches 812A and 812B are interconnected (in the third dimension outside the plane of the paper) and trench 812C is an optional “channel stopper” trench which is located on the outer edge of the termination area. After the trenches have been etched and mask A3 has been removed, a sacrificial oxide layer is formed and removed to repair any crystal damage that occurred during the RIE process. A gate oxide layer 813 is formed on the walls of the trenches 812.
A polysilicon layer 814 is deposited and doped, filling trenches 812 and overflowing onto the surface of the silicon. A fourth, polysilicon mask A4 is deposited on polysilicon layer 814 and patterned (FIG. 8E). Polysilicon layer 814 is etched back into the trenches 812, except for a portion that is allowed to extend from trench 812B onto the field oxide layer 804 in the gate bus area. It is through this extension of the polysilicon layer 814 that electrical contact with the portion of polysilicon layer 814 in the trenches 812 is made.
Mask A4 is then removed, and P-type dopant is implanted and driven in to form P-body regions 816 (FIG. 8F). While this dopant also gets into the polysilicon layer 814, its concentration is too low to create any problems there.
A fifth mask A5 is deposited and patterned to define areas where N-type dopant is to be implanted to form N+ source regions 818 (FIG. 8G). After N+ source regions 818 have been formed and mask A5 has been removed, a borophosphosilicate glass (BPSG) layer 820 is deposited and reflowed. A sixth mask A6 is formed and patterned to define where contact to the substrate (P-body regions 816 and N+ source regions 818) and to the gate (polysilicon layer 814) is to be made (FIG. 8H). P-type dopant is implanted to form P+ body contact regions 821 and then a metal layer 822 is deposited. A seventh mask (not shown) is formed over metal layer 822 and patterned. Metal layer 822 is etched through the seventh mask to form a source metal 822A and a gate bus 822B (FIG. 8I). Optionally, a passivation layer is deposited, and if so an eighth mask (not shown) is formed and patterned to define the source and gate pads, where external contact to the MOSFET will be made.
There are several disadvantages with this process. First, eight masks are required and this leads to considerable complexity and expense. Second, the presence of the field oxide layer 804 and the extension of the polysilicon layer 814 outside the trenches yields a raised topography in the area of the gate bus 822B. This raised area creates problems in photolithography, particularly as the dimensions of these devices extend further into the submicron range. Third, breakdown may occur across the gate oxide at the upper corners of trench 812B polysilicon layer 814 and substrate 802.
Therefore, what is needed is a process that is simpler, yields a flatter topography and avoids the breakdown problem at the upper corners of the trenches.